This page describes technical details of the PiTrex Discrete interface cartridge designed by Kevin Koster. See the [Hardware_Description] for general information.

!! Schematic
{schematic_r1,5,enh,bw,s.png|PiTrex Discrete Schematic|schematic_r1,5,enh,bw.png}
{pitrex_discrete_individual_resistors_r1,5,s.png|Schematic CAD Version|pitrex_discrete_individual_resistors_r1,5.png}

[http://computernerdkev.heliohost.org/pitrex/PCB/R1/PiTrex_Discrete_Individual_Resistors_R1,5.pdf| CAD Schematic PDF]
[http://computernerdkev.heliohost.org/pitrex/PCB/R1/cartconn_Cartridge_Connector.pdf|Cartridge Connector Pinout PDF]

!! Raspberry Pi GPIO Pin Assignments
The Raspberry Pi GPIO is read and written as one 32bit byte. The pin assignments for the Data and Address bus are therefore arranged with respect to the order of bits in the GPIO register, so that the separate Data and Address bytes can be shifted into position using the "<<" shift-left operator, and all written with a single GPIO register write operation.

||||**Description**||**Bit**||**Pin**||**Note**||||
||||D0||16||36|| ||||
||||D1||17||11|| ||||
||||D2||18||12|| ||||
||||D3||19||35|| ||||
||||D4||20||38|| ||||
||||D5||21||40|| ||||
||||D6||22||15|| ||||
||||D7||23||16|| ||||
|||| || || || ||||
||||A0||7||26|| ||||
||||A1||8||24|| ||||
||||A2||9||21|| ||||
||||A3||10||19|| ||||
||||A12||11||23|| ||||
||||A14||12||32|| ||||
||||R/#W||13||33|| ||||
|||| || || || ||||
||||PB6||5||29|| ||||
||||IRQ_LATCH||6||31|| ||||
|||| || || || ||||
||||RDY(#OE)||24||18|| ||||
||||LATCH_EN||25||22|| ||||
||||IRQ||26||37|| ||||
||||#HALT||27||13||Jumper to GND on Pi0||||
||||#D/A||N/A||9||GND on Pi0||||
|||| || || || ||||
||||3V3||N/A||1|| ||||
||||5V||N/A||2|| ||||
||||GND||N/A||6|| ||||

! Unused GPIO Pins
||||**Bit**||**Pin**||**Alt. Function**||**Note**||||
||||0      ||27     ||ID_SD       ||The Raspberry Pi Zero Schematic Notes that this pin should ''only'' be used for EEPROMs used for Pi HAT boards ||||
||||1      ||28     ||ID_SC       ||The Raspberry Pi Zero Schematic Notes that this pin should ''only'' be used for EEPROMs used for Pi HAT boards ||||
||||2      ||3      ||I2C1 SDA    ||I2C Bus ||||
||||3      ||5      ||I2C1 SCL    ||I2C Bus ||||
||||4      ||7      ||GCLK0       ||General-Purpose Clock||||
||||14     ||8      ||UART TXD    ||UART||||
||||15     ||10     ||RXD         ||UART||||
||||28     ||None   ||PCM_CLK     ||Not exposed on GPIO Header. Probably used with audio DAC on other Raspberry Pi boards||||
||||29     ||None   ||PCM_FS      ||Not exposed on GPIO Header. Probably used with audio DAC on other Raspberry Pi boards||||

The UART on pins 8 and 10 can be used for connection to the Linux serial console. Note that the ALT function setting is different between the Raspberry Pi Zero and Raspberry Pi Zero W. For the Raspberry Pi Zero, Linux will use the serial port (UART0) on ALT0 by default. For the Raspberry Pi Zero W, ALT5 (UART1 (Mini UART)). This must be remembered when writing to the GPFSEL1 register to set the function of other pins.

!! Circuit Description
Two flip-flops (IC3, 74HCT74) are clocked from the #E signal which is an inverted version of the interal 1.5MHz clock signal used within the Vectrex, exposed at the Vectrex cartridge port. These control the #OE inputs of the 74LVC646 latching bus buffers, allowing the Address and Data bus outputs to be activated for every other cycle of the Vectrex clock. When not active, these outputs are in a high-impedence state. This action is disabled (assuming that the IRQ LATCH function described below is not used) when the LATCH EN input from the Raspberry Pi is Low. In order to prevent the outputs from being disabled before then end of an #E clock cycle, the Q output of IC3a, which is High when #OE is enabled on the bus buffers, is fed back to the #RST inputs of the flip-flops via D2 and R3, so that operation is only disabled after the active cycle is ended.

''To be continued...''

!!! IRQ LATCH
An additional GPIO output is used for an "IRQ LATCH" signal that is set High instead of LATCH EN after the intended Data and Address bytes have been set on the inputs to the PiTrex. An AND gate ensures that this isn't passed on to the rest of the circuitry until the inverted #IRQ signal, which was already available as an input to the Pi, goes High. Then the process continues as if LATCH EN had been used. This would work for reads as well, if there were cause for that to be triggered by an IRQ (the Pi still has to disable IRQ LATCH before the Data changes though).

!! Cases
The circuit board was designed to allow for mounting within a standard cartridge case, with holes for the corresponding mounting pin locations. However to account for the GPIO header socket, pin jumpers, and DC power socket, significant modifications are required. The mounting pins on the top half of the case may also have to be shortened to avoid fouling on some components.

A [http://computernerdkev.heliohost.org/pitrex/cartcase/|3D printable case design] is available that features these modifications.

Work is continuing on larger-scale production of suitable cases using a circuit board encapsulation process. See [Mechanical_Description]
