> For operation from the Pi, the sequence for reading from the 6522 is as
> follows:
>
>
> --Note: D'/A output always Low when used with the Pi (connected direct to GND)
>
>
> *Pi sets LATCH EN Low.
> *Pi sets Data I/O lines to input mode.
> *Pi sets R/W' output High.
> *Pi sets other Address outputs.
> *When OE' High, Pi sets LATCH EN High (address and data is latched by
>  buffer ICs IC1 and IC2).
> *Data is valid after OE' input goes Low to High (and after that until
>  interface is disabled).
> *Pi sets LATCH EN Low to disable interface.
>
>
>
>
> For Writing:
>
>
> --Note: D'/A output always Low when used with the Pi (direct connection with GND)
>
>
> *Pi sets LATCH EN Low.
> *Pi sets R/W' output Low.
> *Pi sets other Address outputs, and Data outputs.
> *Pi sets LATCH EN High (address and data is latched by buffer ICs IC1
>  and IC2).
> *Data has been written after OE' input goes Low to High (and will
>  be again until interface is disabled).
> *Pi sets LATCH EN Low to disable interface.
>

For operation from 8Bit bidirectional data bus with min. 4x control outputs.
(5V and 3.3V external supply required):
-Control outputs: #OE, LATCH EN, R/#W, #D/A.

External Device = "ED"

Read from 6522:
^^^^^^^^^^^^^^^
*ED sets LATCH EN Low
*--Need to disable IC1 output during address write to buffer!
   -Can't use LATCH EN because this has to go High to latch the
    address. At which point, R/#W will be High (IC1 clashing with
    address inputs from ED).
    -Would need more logic to solve this, so prob. just keep to
     writes and assume they're all that will be required for
     display and sound.
     -"More logic" would be to bring IC1's #OE High when #D/A is
      High.
      -Connect R8 to #D/A?
       -No, directly to Q1 base via diode. So #D/A disables it
        and keeps OE' High when #D/A Low.
        -No, we want it High when #D/A is High
         -OK, so have it connect to Q1's emitter then, so it pulls
          to 3.3v instead of 0v if #D/A is High.
          -Sounds good, but connect R8 to 3.3V instead of 5V (still
           OK for TTL input on 74HCT74)
           -ED should have Max. Vlow = < 0.5V (TTL compat.).
          -Idiot! I'm thinking that Q1 connects to #OE, but it
           actually connects to IC3b #SET!
           -No way to ensure that enough time after address latch
            for data lines to be set to input mode before IC2 #OE
            Low.
            -Except by gating #OE or IC3B #RST.
             -pull #OE High or #RST Low.
              -#OE High via D4.

Take 2:

*ED sets LATCH EN Low.
*ED sets #D/A High (IC2 output disabled).
*ED sets R/#W High.
*ED sets address outputs on data bus.
*When #OE High, ED sets LATCH EN High (address latched).
*ED sets data bus to input mode.
*ED sets #D/A Low.
-When #OE Low, ED sets LATCH EN Low. (may have to cycle count to do this quick enough (within 3 E cycles).
*When #OE goes Low to High, data is valid until next cycle (if LATCH EN not set Low)
 of E (when selected address will match last data)
 -This is a problem because it could cause a write if not
  stopped in time.
  -Prevented by having R/#W as a separate control output from the ED.
   -LATCH EN must be Low within three cycles of E after #OE goes Low
    or invalid data read by ED.
  -Set LATCH EN Low after #OE Low, before data read.

Write to 6522:
^^^^^^^^^^^^^^
*ED sets LATCH EN Low.
*ED sets R/#W Low.
*ED sets #D/A Low.
*ED sets Data outputs on data bus.
*When OE' High, ED sets #D/A High (latches data).
*ED sets address outputs on data bus.
*ED sets LATCH EN High (latches address).
*Data has been written after #OE input goes Low to High (and will be
 again until interface is disabled).
*ED sets LATCH EN Low to disable interface.